The invention pertains to board-on-chip packages, and to methods of forming board-on-chip packages.
A prior art method of forming a board-on-chip package (which can be generally referred to as a die package) is described with reference to FIGS. 1-5. Referring first to FIG. 1, such illustrates a fragment of an assembly 10 comprising an insulative material substrate 12. Substrate 12 can comprise, for example, a circuit board, such as the type known in the art as FR-4(trademark) (which can be obtained from Sumitomo of Japan), or BCB(trademark) (which can be obtained from Toppan of Japan).
Substrate 12 comprises a top surface 13 and slits 18 extending therethrough. Circuitry 16 is formed on top of surface 13. Circuitry 16 and slits 18 form repeating patterns across top surface 13. The repeating patterns define separate units 19, 21 and 23, each of which ultimately forms a separate board-on-chip package.
Referring to FIGS. 2-4, an enlarged segment of substrate 12, corresponding to unit 21, is shown in three different views. FIG. 2 is a top view similar to the view of FIG. 1, FIG. 3 is an end view, and FIG. 4 is a view along the line 4xe2x80x944 of FIG. 3. Substrate 12 is inverted in the view of FIG. 3 relative to the view of FIGS. 1 and 2. Accordingly, surface 13 (referred to as a top surface in referring to FIGS. 1 and 2) is a bottom surface in the view of FIG. 3. In referring to FIG. 3, surface 13 will be referred to as a first surface.
Substrate 12 comprises a second surface 15 in opposing relation relative to first surface 13. A semiconductive material-comprising chip (or die) 14 is adhered to surface 15 via a pair of adhesive strips 20. Strips 20 can comprise, for example, tape having a pair of opposing surfaces 22 and 24, with adhesive being provided on both of such opposing surfaces. Strips 20 typically comprise insulative material. Wire bonds 28 (only some of which are labeled in FIG. 2) extend from circuitry 16 and through slit 18 to electrically connect circuitry 16 to bonding pads 25 (only some of which are labeled in FIG. 2) associated with chip 14, and to accordingly electrically connect circuitry 16 with circuitry (not shown) comprised by chip 14. (The wire bonds and bonding pads are not shown in FIG. 4 for purposes of clarity in the illustration.)
FIG. 5 illustrates further processing of the assembly 10. Specifically, FIG. 5 illustrates units 19 and 21 of FIG. 1 after a first encapsulant 40 is provided over wire bonds 28, and a second encapsulant 42 is provided over chips 14 associated with units 19 and 21. First and second encapsulants 40 and 42 can comprise the same material and preferably comprise an insulative material, such as, for example, cured epoxy.
Conductive balls 31 are formed over portions of circuitry 16 (shown in FIGS. 1 and 2) to form a ball grid array over circuitry 16. Such array can subsequently be utilized to form a plurality of interconnects from circuitry 16 to other circuitry (not shown). Conductive balls 31 can be formed of, for example, tin, copper or gold.
Substrate 12 is subjected to a singulation process which separates units 19 and 21 from one another, and thus forms individual board-on-chip packages from units 19 and 21. The singulation process can include, for example, cutting through encapsulant 42 and substrate 12.
A problem which can be associated with board-on-chip packages is that the chip can heat during use. The heating can damage electrical components associated with the chip. It would be desirable to develop alternative board-on-chip packages which alleviate such heating.
In one aspect, the invention encompasses a board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A semiconductive-material-comprising die is adhered to the substrate and electrically connected to the circuitry with a plurality of electrical interconnects extending through the opening. A metal foil is in physical contact with at least a portion of the die.
In another aspect, the invention encompasses another embodiment board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A semiconductive-material-comprising die is adhered to the substrate and electrically connected to the circuitry with a plurality of electrical interconnects extending through the opening. The die has a first surface facing the substrate and a second surface in opposing relation to the first surface. The die further comprises a sidewall surface extending between the first and second surfaces. A thermally conductive material is in physical contact with at least one of the die first surface, second surface and sidewall surface. The thermally conductive material has a thermal conductivity under specified conditions equal to or greater than the conductivity of elemental copper under the same specified conditions.
In yet another aspect, the invention encompasses a method of forming a plurality of board-on-chip packages. An insulative substrate is provided. Such substrate has a repeating circuitry pattern thereon, and a plurality of openings therethrough. The openings are in a one-to-one correspondence with individual of the repeated circuitry patterns. A plurality of semiconductive-material-comprising dies are adhered to the substrate. Circuitry supported by the dies is electrically connected with the circuitry on the substrate utilizing a plurality of electrical interconnects extending through the openings. A metal foil is joined to the substrate and extended over the plurality of dies. The substrate and metal foil are cut to form singulated die packages comprising a single die, a portion of the substrate having a single repeated pattern of the circuitry, and a portion of the metal foil.